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128 Channel Isolated Digital Input / Interrupt Module
DP-VXI-3117
DP VXI 3117 provides 128 isolated channel digital inputs for sensing DC levels and edge transitions of upto 48VDC. The input level selection for 5 (TTL / CMOS compatible), 12, 24 or 48V is made through on-board jumper selection. The debounce feature is programmable for a period of 2msec to 2147 sec. in binary increments. Channel groups 1 to 32, 33 to 64, 65 to 96 and 97 to 128 can each have a unique programmed debounce period, provided the ratio of clock period between groups does not exceed 32,768.
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Clock Signal Generators
Optellent offers a range of clock signal generators providing clean reference clock signals up to 32 GHz.
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PXI Express Hybrid Peripheral Module
SMT712
Sundance Multiprocessor Technology Ltd.
The SMT712 is a PXI Express (opt. Hybrid) Peripheral Module (3U), which integrates two fast 12-bit DACs, 2 banks of 1GByte DDR2 memory each, a clock circuitry and a Virtex5 Xilinx FPGA, under the 3U format.
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Online Monitoring Systems
RAEM system is the latest IIoT-AE product series for remote unattended acoustic wave (acoustic emission) long term monitoring applications. There are a few types of RAEM series products available:RAEM1 is a single channel full function version of RAEM.RAEM1-6 is a 6-channel integrated clock synchronized version.RAEM2 is a single channel time trigger power saving compact version.The Qingcheng IoT Cloud platform is an cloud platform for RAEM and IoT devices to upload or download data, to display AE waveform, parameters and alarm information, to remote read and write devices, to send alarm notifications to users via SMS and emails and more.
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2-Channel 200 MHz A/D with 766 DDCs, Kintex UltraScale FPGA - XMC
Model 71865
- Jade Xilinx Kintex UltraScale FPGA Products and Navigator Design Suite Software Video- Jade Xilinx Kintex UltraScale FPGA Family Brochure- Complete software radio receiver solution for extremely high-channel-count applications- Uses Xilinx Kintex UltraScale KU035 FPGAs- Two 200 MHz 16-bit A/Ds- Four wideband DDCs (digital downconverters)- Up to 762 narrowband DDCs- Sample clock generation and synchronization to an external system reference- PCI Express (Gen. 1, 2 & 3) interface up to x8- VITA 42.0 XMC compatible with switched fabric interfaces- Ruggedized and conduction-cooled versions available- Synchronize up to eight modules with Model 7893 System Synchronization and Distribution Amplifier - PCIe
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2-Ch 500 MHz A/D with DDC & 2-Ch 800 MHz D/A with DUC, Virtex-6 FPGA - XMC
Model 71651
- Complete radar and software radio interface solution- Supports Xilinx Virtex-6 LXT and SXT FPGAs- Two 500 MHz 12-bit A/Ds- Two multiband DDCs (digital downconverters)- Two 800 MHz 16-bit D/As- One DUC (digital upconverter)- Multiboard programmable beamformer- Up to 2 GB of DDR3 SDRAM or 16 MB of QDRII+ SRAM- Sample clock synchronization to an external system reference- Front panel clock/sync bus for multimodule synchronization- PCI Express (Gen. 1 & 2) interface up to x8- Optional LVDS connections to the Virtex-6 FPGA for custom I/O- Synchronize up to eight modules with Model 7893 System Synchronization and Distribution Amplifier - PCIe
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MODEM ELIMINATOR
The UDC-ME allows two DTE devices (such as routers) to communicate within proximity of each other. The UDC-ME transmits data bi-directionally at clock rates of 1.2k up to 3.072Mbps between DTE devices. The unit is equipped with two interface slots that allow a host of serial interface cards to be utilized. The serial interface cards available are RS-232, RS-422/449, RS-530, X.21, V.35 and HSSI. The Serial Interface cards are interchangeable and may be mixed such as RS-232 to V.35 thus eliminating the need for an interface converter or changing expensive serial cards on a DTE device such as a router.
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4-Channel 500 MHz A/D and 4-Channel 800 MHz D/A with Virtex-6 FPGA - 6U VPX
Model 58650
- Complete radar and software radio interface solution- Supports Xilinx Virtex-6 LXT and SXT FPGAs- Four 500 MHz 12-bit A/Ds- Two DUCs (digital upconverters)- Four 800 MHz 16-bit D/As- Up to 4 GB of DDR3 SDRAM; or: 64 MB of QDRII+ SRAM- PCI Express (Gen. 1 & 2) interface up to x8- Sample clock synchronization to an external system reference- LVPECL clock/sync bus for multiboard synchronization- Optional user-configurable gigabit serial interface- Optional LVDS connections to the Virtex-6 FPGA for custom I/O- Ruggedized and conduction-cooled versions available- Synchronize up to eight modules with Model 7893 System Synchronization and Distribution Amplifier - PCIe
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Timing, Logic & Memory
Offering an extensive portfolio of products for programmable clocks, clock generation and distribution, standard logic and memory (Flash, EEPROM and SRAM) across various applications.
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Clock And Trigger Synchronization System
CLKSYNC-50
CLKSYNC-50 is a clock and trigger distribution system that provides multiple, independent copies of clock and trigger signals for multi-channel, Giga-sample ADC and DAC boards. Up to sixteen independent ADC or DAC clocks and triggers are synchronized.
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50 MHz to 2.2 GHz, GPS-Disciplined OCXO, Reconfigurable USRP Software Defined Radio Device
783926-01
50 MHz to 2.2 GHz, GPS-Disciplined OCXO, Reconfigurable USRP Software Defined Radio Device - The USRP-2950 provides an integrated hardware and software solution for rapidly prototyping high-performance wireless communication systems. With the flexible hardware architecture and the LabVIEW unified design flow, researchers can prototype faster and significantly shorten time to results. You can prototype a wide range of advanced research applications that include multiple input, multiple output (MIMO); synchronization of heterogeneous networks; LTE relaying; RF compressive sampling; spectrum sensing; cognitive radio; beamforming; and direction finding. The USRP-2950 is equipped with a GPS-disciplined 10 MHz oven-controlled crystal oscillator (OCXO) reference clock. GPS disciplining delivers improved frequency accuracy and synchronization capabilities.
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4 Channel 24.5~ 29.0 Gb/s Pulse Pattern Generator and Error Detector
CA9808
The UC INSTRUEMNTS CA9808 4 Channel 24.5 ~ 29.0 Gb/s (100Gb/s) Pulse Pattern Generator and Error Detector is a high performance, flexible and cost effective four channel Pulse Pattern Generator and Error Detector that can operate from 24.5 Gb/s to 29 Gb/s each Channel. 4 channel 29.0 Gb/s make it total up to over more than 100 Gb/s testing capacity. It is also a standalone Bit Error Rate test solution that incorporates an internal full rate clock synthesizer.
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10 Channel ADC FMC Module
ADCFN10-DC – HPC
Sundance Multiprocessor Technology Ltd.
The RFM-ADCFN10 is a ten channel Analog to Digital converter FMC which complies with VITA 57.1-2010. Each channel provides single-ended analog input and 16-bit single-ended output with 20-105MHz sampling speed based on ADI AD9650. Both AC and DC coupled input are supported. Single-ended external clock, differential external clock or an internal clock from the FMC carrier board can be selected at the FMC for the AD converter through fine clock generator ADI AD9518-3.
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Virtual Clock for Application Testing
Time Machine
Time Machine provides software virtual clocks that enable you to time travel your applications into the future or the past, facilitating time shift testing on your date and time sensitive application logic, such as month end, quarter end, year end processing, billing cycle, work flow, regulatory go live, and policy life cycle.
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FPGA Mezzanine Card
FMC116
The FMC116 is a 16-channel ADC FMC daughter card which is fully compliant with the VITA 57.1-2008 standard. The FMC116 provides 16 A/D 14-bit 125Msps channels which can be sampled by an internal clock source (optionally locked to an external reference) or an externally supplied sample clock. A trigger input for customized sampling control is also available.
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Advanced Measurement Package For M8000 Series Of BERT Test Solutions
M8070ADVB
The M8070B system software for the M8000 Series of BER Test Solutions can be enhanced by additional software packages, such as M8070ADVB or M8070EDAB to get the best out of the M8040A, M8020A and M8030A J-BERT platforms.The M8070ADVB Advanced Measurement package offers advanced features like automated jitter tolerance test and parameter sweeps, eye diagram measurement or the integration of external equipment such as electrical and optical clock recovery or error analysis using a real-time scope.
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Y/t Recorder Software Module
Metra Mess- und Frequenztechnik in Radebeul e.K.
*Time graph display*Level display of vibration acceleration*VM-PLOT+ also for velocity and displacement*RMS, positive, negative and unsigned peak values, slow changing instantaneous value*Two time axes for clock time and time since start*Up to four signals per window*One VM-Plot license can be operated simultaneously up to four times with different settings *External Messengers*Offline measurement
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1U 19” Edge Server With 4th Gen Intel® Xeon® Processor Scalable Family Processor
MECS-7120
- 1U 19” Edge Server with 4th Gen Intel® Xeon® Processor Scalable Family Processor- 6x DDR5 DIMMs, 4800MT/s (6 channels, 1DPC)- On-board 2x 25G SFP28 Ethernet ports- 1U 19’’ rackmount form factor for telecom infrastructure deployment- RunBMC with AST2600, IPMI v2.0/Redfish compliant- Optional clock module to provide time sync from GNSS- Designed for 5G: DU, DU+CU, DU+CU+MEC, MEC, uCPE, industrial edge computing
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8-Channel 250 MHz A/D with DDC, Kintex UltraScale FPGA - 6U VPX
Model 57131
- Jade Xilinx Kintex UltraScale FPGA Products and Navigator Design Suite Software Video- Jade Xilinx Kintex UltraScale FPGA Family Brochure- Ideal radar and software radio interface solution- Supports one Xilinx Kintex UltraScale FPGAs- Eight 250 MHz 16-bit A/Ds- Eight multiband DDCs (digital downconverters)- 5 GB of DDR4 SDRAM- Sample clock synchronization to an external system reference- LVPECL clock/sync bus for multiboard synchronization- PCI Express (Gen. 1, 2 & 3) interface up to x8- Optional LVDS and gigabit serial connections to the FPGA for custom I/O- Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX™ System Specification)- Ruggedized and conduction-cooled versions available
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ARM LPC2364 Board
MS 1541
- 128KB On chip Flash- 16*2 line LCD Module interface- Two CAN channel at 1MPBS- Ethernet interface which supports 10/100 MBPS- Full Modem RS232 interface- RS485 interface- RTC (Real Time Clock)- 2048 bits serial EEPROM with data protect and sequential read.- 24 ULN outputs of 12V level.- Eight 110V DC inputs interface.- Six digital inputs interface- Four on board keys interface- Power delay circuit for external use- ON board inspection circuit
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2-Ch 500 MHz A/D with DDC & 2-Ch 800 MHz D/A with DUC, Kintex UltraScale - 6UVPX
Model 57851
- Jade Xilinx Kintex UltraScale FPGA Products and Navigator Design Suite Software Video- Jade Xilinx Kintex UltraScale FPGA Family Brochure- Complete radar and software radio interface solution- Supports Xilinx Kintex UltraScale FPGAs- Supports VITA-49.2 VITA Radio Transport standard- Two 500 MHz 12-bit A/Ds- Two multiband DDCs (digital downconverters)- One DUC (digital upconverter)- Two 800 MHz 16-bit D/As- 5 GB of DDR4 SDRAM- Sample clock synchronization to an external system reference- LVPECL clock/sync bus for multimodule synchronization- PCI Express (Gen. 1, 2 & 3) interface up to x8- Optional LVDS and gigabit serial connections to the FPGA for custom I/O- Compatible with several VITA standards including: VITA-46, VITA-48 and VITA-65 (OpenVPX™ System Specification)- Optional 400 MHz 14-bit A/Ds- Ruggedized and conduction-cooled versions available- Synchronize up to eight modules with Model 7893 System Synchronization and Distribution Amplifier - PCIe
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High Performance 50 MHz Dynamic Digital I/O PXI Subsystem
GX5960 Series
The GX5960 digital subsystem represents the highest level of performance available for PXI-based digital instrumentation and features high performance pin electronics and a timing generator / sequencer in a compact, 6U PXI form factor. The GX5960 series consists of the GX5961 clock generator board with 16 driver / sensor channels and the GX5964 driver / sensor board which supports 32 bi-directional I/O channels. Up to 528 digital I/O channels can be supported by the GX5960 digital subsystem. Each digital channel features a wide drive / sense voltage range of -14 V to +26 V (maximum swing of 24 volts) which can be individually programmed for a drive hi, drive lo, sense hi, sense lo, and a load value (with commutation voltage level) – offering the user complete flexibility when creating test programs and fixtures for multiple UUTs. In addition, each channel offers a parametric measurement unit (PMU) for DC measurements.
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High-Speed Clock Generator - PCIe
Model 7894
Provides sample clock for up to four separate PCIe Cobalt or Onyx boards, Locks to user-supplied 10 MHz reference clock or on-board reference, OCXO provides an exceptionally precise clock.
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SSA-J Precision Clock Jitter Analysis Software
E5001A
To meet the demanding needs of today's advanced digital communication systems, Keysight offers Precision Clock Jitter Analysis software (E5001A SSA-J) for more precise and accurate characterization and evaluation of clock-signal jitter.
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Synthesized Clock Generator
CG635
Stanford Research Systems, Inc.
The CG635 generates extremely stable square wave clocks between 1 µHz and 2.05 GHz. The instrument''s high frequency resolution, low jitter, fast transition times, and flexible output levels make it ideal for use in the development and testing of virtually any digital component, system or network. Clocks from 1 µHz to 2.05 GHz. Random jitter <1 ps rms. 16 digits of frequency resolution. 80 ps rise and fall times. CMOS, PECL, ECL, LVDS & RS-485. Phase control and time modulation. PRBS for eye-pattern testing. OCXO and rubidium timebase.
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Marine Ballast Water Analyzer
9017
Developed specifically for the demands of marine environments, OI Analytical's new Model 9017 Marine Ballast Water Analyzer was engineered to meet the stringent United States Coast Guard (USCG) standards. The 9017 monitors and controls total chlorine and residual oxidants around the clock, while connected to a Ballast Water Management System with user-programmable cycle times and alarms.
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3-Ch 200 MHz A/D with DDC & 2-Ch 800 MHz D/A with DUC, Virtex-6 FPGA - 6U VPX
Model 57621
- Complete radar and software radio interface solution- Supports Xilinx Virtex-6 LXT and SXT FPGAs- Three 200 MHz 16-bit A/Ds- Three multiband DDCs (digital downconverters)- One DUCs (digital upconverters)- Two 800 MHz 16-bit D/As- One multiboard programmable beamformers- 2 GB of DDR3 SDRAM; 32 MB of QDRII+ SRAM- PCI Express (Gen. 1 & 2) interface up to x8- Sample clock synchronization to an external system reference- LVPECL clock/sync bus for multiboard synchronization- Optional LVDS connections to the Virtex-6 FPGA for custom I/O- Ruggedized and conduction-cooled versions available- Synchronize up to eight modules with Model 7893 System Synchronization and Distribution Amplifier - PCIe
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Semiconductors
Meets SDIO card v2.0 specificationSupports SDIO SPI, 1-bit, and 4-bit SD modesHost clock rate from 0-50 MHzSingle SDIO function interfaceSD commands processed in hardwareReset output on completion of initializationIndication of high speed and high power enabling to application logicMaximum block size supported is 1024 bytesThree I/O mode selection pinsCRC7 and CRC16 modulesSupports direct R/W (IO52) and extended R/W (IO53) commandsAPB bus interfaceParallel bus interfaceStandard 8051 split bus interfaceGeneric 8051 bus interfaceUART interface
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Low Profile PCI Express 2-Port
7204ec
The 7204ec low-profile PCI Express serial interface provides two serial ports configurable for RS-422 or RS-485. Each serial port features an ultra high-speed UART, flexible clock prescalar, and large 256-byte Tx/Rx FIFOs allowing the adapter to support the widest range of standard and non-standard baud rates exceeding 1 Mbps. These features make the 7204ec ideal for data intensive applications that require reliable, ultra-fast throughput rates.
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FMC-HPC ADC Board
FMC121
Sundance Multiprocessor Technology Ltd.
The FMC121 provides two 16-bit A/D channels up to 1Gsps and two 16-bit D/A channels up to 1.4 Gsps data rate with a 2.8 GSPS update rate. The design is based on Texas Instruments’ ADS54J60 Analog-to-Digital converter and Texas Instruments DAC39J84 Digital-to-Analog converter. The sample clock can be supplied externally through a coaxial connection or supplied by an internal clock source (optionally locked to an external reference) for multi-channel synchronization. An external trigger input is available for timing synchronization. The FMC121 is mechanically and electrically compliant to the FMC standard (ANSI/VITA 57.1).
