Verification IP
test and verify SoC's protocols and interface buses.
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3U Format CompactPCI (CPCI) Bus IP Carrier
CPCI-SIP-2
The CPCI-SIP is a 3U format CompactPCI (CPCI) bus IP carrier. The CPCI-SIP-2 provides mechanical support and the electrical interfaces for two single width IP modules, or a double width IP module. Multiple CPCI-SIP-2 boards may be installed in a single system.
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Communication Network Lab (5G, 4G, 3G, 2G, IP, TDM)
GL’s End-to-End Wireless Network Simulation Test Suite provides you an advanced full-fledged “Live Network” at your company premises in any customized package to suit test requirements.
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Specialized Extender Card Testing IP Modules
IP-Debug-Bus
IP-Debug-Bus is a specialized extender card which is optimized for testing IP Modules. The bus signals are all accessible via test points. The testpoints include multiple ground locations and .025 sq. posts for ease of connection to your logic analyzer or scope. The testpoints are labeled for easy identification
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FPGA Image Processing (IP) Development Kit
ProcVision
Gidel’s Vision Pro Development Kit is an optimal solution for developing,validating, demonstrating and evaluating Image Processing (IP) andpipeline designs on FPGA.The suite is designed to provide a complete and convenient envelop enablingthe developer to focus strictly on the proprietary image processingdesign. The entire Vision Pro flow is within a single FPGA, independentof the final target application(s). The Vision Pro flow is composedof a pipeline that streams simulated data to the user image processingdesign under test (DUT) and then captures the design’s output streamfor displaying, storing, analysis and/or co-processing on host software.The entire process is performed on a single FPGA without the need foradditional peripheral connectivity or tools.Vision Pro suite is plug-and-play enabling the developer to begin at oncethe IP design development and validation. A simple design example providesthe developer immediate hands-on familiarization with the systemflow and supporting tools. The final design can be ported to any IntelFPGA device or other vendors’ devices (FPGA or ASIC) by replacing basiclibraries. To significantly reduce compilation time, initial design developmentmay be on a small FPGA device and later compiled for the targetdevice(s). The target implementation may use any FPGA board. For a fullImaging/Vision system solution, Gidel offers a number of off-the-shelfgrabbers and FPGA accelerators that are designed to utilize these imageprocessing blocks and Gidel Imaging Library (GIL).
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Handheld Digital Multimeter, 4 digit, with IP 67
U1242C
The strong and solid U1240C Series handheld digital multimeters(DMMs) are the tools technicians or industrial test engineers use to perform their work confidently and efficiently. Designed for handheld users working in various environments, the U1240C series is certified to IP 67 and capable to withstand up to 3-meter (10 feet) drop to suit harsh working environments. The U1240C handheld DMM scan even work longer for you with up to 400 hours of battery life. With the built-in LED flashlight, the U1240Chandheld DMM sallow users to single-handedly illuminate test area.
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PC/104+ Card with 4 IP Slots
PC104p4IP
If you want to use IndustryPack modules with your PC/104+ or PC/104-Plus system, the PC104p4IP is the choice for you. The PC104p4IP combines features you need with simplicity and speed. Up to 4 IP modules can be installed. Standard 16 bit IPs plus 32 bit, and double wide modules fit right in. Each slot has independent operation - control, clocking, IO, power filtering and protection. The PC104p4IP is highly integrated with the PCI and IP interfaces closely coupled within the same FPGA.
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Matrix Code Verification Systems
REA MLV-2D
The REA MLV-2D is a matrix- and barcode verifier which has been developed in conformance to international standards. The measurement uses defined angeles distance and illuminations to achieve repeatable results and quality information.
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Modular TDM / IP Split Mount Radio System
CFIP PhoeniX M
CFIP PhoeniX M split mount system consists of PhoeniX M IDU and PhoeniX ODU (XPIC functionality supported). PhoeniX M IDU provides up to 63E1 and 2xSTM-1 bringing the total maximum capacity to 348 Mbps full duplex.
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Real-time IP network measurements
IPProbe
Real-time network measurements for multiple IP interfaces. Detection of Packet loss, IAT (Inter Arrival Time), Delay, Bitrate and ETR290 problems. Stable packet generation and receiving is a key feature required in any modern IPTV environment. Any irregularity and/or discontinuity in this packet stream means buffering problems or losing frames. IP jitter provides a means to see the distribution and stability in the IP stream.
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EBIRST 50-pin D-type Verification Fixture
93-005-101
The 93-005-101 50-pin D-type Verification Fixture is an accessory for the eBIRST range of USB controlled test tools capable of performing automated path resistance tests on Pickering Interfaces switching solutions. Each tool simply interfaces with the switching system's connector so a test can be run using the supplied Windows-based software.
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Torque Verification
90229
SDI’s 90229 is designed for calibrating tools used to apply torque including electric and pneumatic power tools, torque sensors, hand and click wrenches. The strain gage based reaction torque sensors in the bench-mount housing remain stationary while torque is applied. The housing dis-assembles by removing two snap pins, allowing the user to easily change socket sizes and capacities.
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IP Fax/ Modem Testing
To successfully deploy fax services requires extensive network design, test and traffic engineering. Test equipment can prove valuable in this process, if it can: Generate and receive fax signals in bulk over wired and wireless networks, monitor and distinguish fax signals in real time for traffic engineering and network design purposes, and analyze fax signals after capture for troubleshooting failed or poorly handled calls.
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PCI card with 3 IP sites
PCI3IP
The PCI compatible PCI3IP design adds 3 Industrypack compatible slots to your PCI host. The PCI3IP acts as an adapter, converter, carrier, or bridge between the PCI bus and your IndustryPack hardware. The PCI3IP is a half size PCI card with 3 IP sites; compatible with the smallest chassis and the tallest processors that prevent full size solutions.
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Portable Sequence Generator for Verification, Firmware & Validation
ISequenceSpec
The complexity of modern SoC has raised the requirement for HW/SW co-simulation to catch the bugs from the early design stage. There is lack of common set of sequences which can be shared across the teams. ISepenceSpec helps design teams to generate the unified test and programming sequences in UVM and Firmware from the specification. ISequenceSpec uses the register information from importing the standard formats like IP-XACT, SystemRDL, XML. User can define the test sequences in a simple editor, and then generate the unified test sequences from verification to validation.
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Develop - Simulate - Validate JTAG / IJTAG based IP
NEBULA
You, your vendors and your customers being able to use one common interface to control and observe on-chip IP, resources and instruments. The figure below shows an example IC. The new IEEE 1149.1-2013 standard supports an init-data register for configuring the analog paramaters of I/O as well as controlling on-chip PLLs. The standard further extends this by defining in BSDL user test data registers or 'scan chains'. These registers enable the ability of generic software to control and observe mission mode IP and instruments simply by describing the register interface in BSDL.
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Foundation IP
TSMC
Our Foundation IPs embed power management features (multi-Vt/multi-channel libraries, multi-VDD characterization, integrated power-switches, source-biasing…) which allow designers to explore the SoC architecture. Optimal configurations can be generated to meet the application’s Performance, Power and Area constraints. We also complement our offering to reach best-in-class Energy Efficient SoC by serving Always-On power-domains with a dedicated offer, optimized to achieve the ultra-low-power requirements of battery-operated devices in sleep mode.
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RISC-V Processor IP Core Evaluation Kit
The EMSA5 demo platform is an ideal tool for evaluating the RISC-V processor IP core EMSA5. It contains an Artix®-7 35T FPGA Arty evaluation board with implemented EMSA5-IP core. Thanks to the included peripherals and expansion interfaces, the kit is ideal for numerous applications. The kit is JTAG programmable and includes Quad SPI Flash, a JTAG port, 10/100 Mb/s Ethernet and a USB-UART bridge, four Pmod connectors and an Arduino Shield expansion connector.
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IP Surveillance Camera
ENVIROMUX-IPCAM
View and control the camera from the ENVIROMUX web interface, the camera web interface, included software, or with a compatible cell phone. With the ENVIROMUX-2D/5D/16D, a triggered snapshot can be forwarded in alert e-mails. A snapshot can be triggered by any programmed event (motion detection, door open/close, glass break, smoke, liquid detection, etc.). Image sensor: 1/4" progressive scan CMOS sensor. Video Streaming: simultaneous Motion JPEG and MPEG-4. Frame rate: 30fps at 640x480 (VGA) resolution. Lens: F2.0, 4.0 mm (0.16 in). RJ45 connector. Wireless models: wireless IEEE 802.11 b/g up to 54 Mbps. Regulatory approvals: CE, FCC, RoHS.
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IP X1, X2 Chamber - Drip/IP Test Chamber
The drip box testing chambers from Weiber are rain test machines used for testing the outer protection of signal devices, external lighting equipments and car lamps etc. The equipment finds widespread usage in electronics industry and automotive and aerospace industries and is commonly employed for quality testing of products. The test chamber comprises of the guiding upright column, a drip mold, a rotating sample table with adjustable speed and a level meter to allow observation of the level in the drip mold. The equipment uses high quality construction materials for a sturdy construction and is designed for safe and reliable operation. The guiding upright column is made up of high-quality, plastic coated square steel pipe, whereas the drip mold is made up of high-quality stainless steel finish plate undergoing knurling.
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A Visual And Interactive Tool For Pre-CTS Analysis And Post-CTS Verification
ConTree
ConTree is a clocking logic visualization, analysis and verification tool. It is used for both pre-CTS clocking analysis as well as post-CTS clock tree verification.
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Wireless IP Surveillance Camera
ENVIROMUX-IPCAM-W
View and control the camera from the ENVIROMUX web interface, the camera web interface, included software, or with a compatible cell phone. With the ENVIROMUX-2D/5D/16D, a triggered snapshot can be forwarded in alert e-mails. A snapshot can be triggered by any programmed event (motion detection, door open/close, glass break, smoke, liquid detection, etc.). Image sensor: 1/4" progressive scan CMOS sensor. Video Streaming: simultaneous Motion JPEG and MPEG-4. Frame rate: 30fps at 640x480 (VGA) resolution. Lens: F2.0, 4.0 mm (0.16 in). RJ45 connector. Wireless models: wireless IEEE 802.11 b/g up to 54 Mbps. Regulatory approvals: CE, FCC, RoHS.
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ARINC 664 P7 IP Core
iWave’s ARINC 664 P7 IP is an Ethernet Technology that provides a deterministic network to build an ARINC 664 P7 end system with guaranteed service to each subscriber with free access to the network. This protocol offers dedicated bandwidth for each node with guaranteed quality of service. iWave offers high integrity and redundancy management, as well as UDP/IP, profiled communication layer implemented in hardware.
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Audio IP
We provide high-performance, compact, low power and customizable audio analog mixed-signal IP in leading foundry processes, including a wide range of ADC, DAC, CODEC and Voice Activity Detectors.
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AV over IP
Innovative and award-winning solutions for capturing, managing and distributing audio and video signals over an IP network.
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Standalone ASI To IP Converter
DTE-3120
DekTec's standalone power-over-ethernet enabled ASI to IP Converter, allowing zero-jitter transmission of Transport Streams to IP networks.
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4x4 VGA + Audio Matrix Switch with UTP Output and IP Control
VSM-I-A-4-JA4
Switch up to 4 VGA inputs to 4 VGA outputs with independent audio routing. Additional RJ45 output connectors provide extended output up to 1000 ft (305 m) over a single UTP cable (with compatible URA receivers). 550 MHz bandwidth supports resolutions beyond 1920x1200.
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Enhance Transactional Universal Verification Methodology (UVM) testbenches
TrekUVM
TrekUVM automatically generates self-verifying test cases that run in existing transactional testbenches, including those compliant with the Universal Verification Methodology (UVM) standard. This verifies your chips more quickly and more thoroughly than using UVM alone to generate transactions. TrekUVM's generated test cases target all aspects of full-chip verification and work in a variety of different environments.
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LSI Functional Verification Services
SpecInsight
The keys to functional verification are “verification strategy” and “highly complete verification item extraction.” Our functional verification services emphasize highly complete verification item extraction while also generating test benches and functional scenarios, random verification, and even functional coverage to meet customer demands by providing these services from a wide variety of angles. By implementing functional verification on the RTL and C models designed by customers from a third-party perspective, we improve quality of customers’ circuits.
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Phase Verification Bridges
5002
Clarke-Hess Communications Research
The Model 5002 Phase Verification Bridge set comprises passive devices that are used in conjunction with Model 5500-2 Phase Standard and an output null indicator such as a true rms voltmeter, an oscilloscope or a wave analyzer to verify that the Phase Standard is continuing to operate within its specified phase accuracy limits.
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MCB Thermal Verification Test Bench
The test system is a special version of the thermal test test system in the sense that the test jig is primarily designed to hold and connect multi pole MCBs for thermal verification so that each pole can be verified to trip within the IEC time band after the MCB has been riveted. This test ensures the trip verification of MCB so as to trip all the 4 poles at once when overload is detected in one single pole. In short, this is a verification-only bench.
