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Compiler
translates a programming language to machine code.
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C/C++ Source Code Analysis
CODECHECK
CodeCheck is a programmable tool for checking all C and C++ source code on a file or project basis. CodeCheck is input compatible with all variants of Standard K&R C, Standard ANSI-C/C++, and all C and C++ compiler vendors. We support GCC-GNU Open Source C/C++ compilers. CodeCheck is designed to solve all of your Portability, Maintainability, Complexity, Reusability, Quality Assurance, Style Analysis, Library/Class Management, Code Review, Software Metric, Standards Adherence, and C++ Corporate Compliance Problems.
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FPGA Image Processing (IP) Development Kit
ProcVision
Gidel’s Vision Pro Development Kit is an optimal solution for developing,validating, demonstrating and evaluating Image Processing (IP) andpipeline designs on FPGA.The suite is designed to provide a complete and convenient envelop enablingthe developer to focus strictly on the proprietary image processingdesign. The entire Vision Pro flow is within a single FPGA, independentof the final target application(s). The Vision Pro flow is composedof a pipeline that streams simulated data to the user image processingdesign under test (DUT) and then captures the design’s output streamfor displaying, storing, analysis and/or co-processing on host software.The entire process is performed on a single FPGA without the need foradditional peripheral connectivity or tools.Vision Pro suite is plug-and-play enabling the developer to begin at oncethe IP design development and validation. A simple design example providesthe developer immediate hands-on familiarization with the systemflow and supporting tools. The final design can be ported to any IntelFPGA device or other vendors’ devices (FPGA or ASIC) by replacing basiclibraries. To significantly reduce compilation time, initial design developmentmay be on a small FPGA device and later compiled for the targetdevice(s). The target implementation may use any FPGA board. For a fullImaging/Vision system solution, Gidel offers a number of off-the-shelfgrabbers and FPGA accelerators that are designed to utilize these imageprocessing blocks and Gidel Imaging Library (GIL).
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ARM Development Studio 5
DS-5
ARM DS-5 is the tool-chain of choice for software developers who want to fully realize the benefits of the ARM Architecture. Comprising features such as the best-in-class ARM Compiler, powerful OS-aware debugger, system-wide performance analyzer, and real-time system simulator, DS-5 is an integrated development environment that assists engineers in delivering optimized and robust software for ARM processor-based ASICs and ASSPs.
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Compiler Test & Validation Suite
SuperTest
SuperTest is the test and validation suite for C and C++ compilers that has tracked the (ISO) language specifications for more than 30 years. It is a complete validation environment with: A huge library of hand-written test, A large body of generated tests, A framework to easily set-up and run compiler validations.
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Human Vibration Management Software
HVManager
HVManager is a Risk Assessment and Recordkeeping software tool for reporting Vibration measurements and predicting Personal Exposure Levels. It provides reports of vibration measurement data from hand-arm and whole-body measurements acquired from the Larson Davis HVM100 Human Vibration Meter and produces vibration database records by tool type and serial number. HVManager also compiles cumulative predicted vibration exposure levels from any combination of tools and task durations taken from the measurement database.
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Boundary-Scan DIMM Socket Tester
ScanDIMM
Maximizing test coverage is an important piece in test procedure development. Unfortunately, not all designs have the necessary requirements in place to accommodate boundary-scan test methods on memory devices. ScanDIMM digital socket test modules are designed to overcome such limitations when testing DIMM sockets utilizing boundary-scan test techniques.ScanDIMM modules provide the capability to instantly turn any DIMM socket into a fully compliant IEEE-1149.1 device. Integration is as simple as assigning the included BSDL file to the reference designator of the target socket and compiling test vectors.In multi-socket systems, multiple ScanDIMM modules can be linked to provide even greater boundary-scan test depth.
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PathWave RFIC Design (GoldenGate)
Early in the RFIC design phase, monitoring system IC specifications such as EVM via RF simulation is a must. Simulations include effects of layout parasitics, complex modulated signals, and digital control circuitry. With PathWave RFIC Design, you can simulate in both the frequency and time domain and bring your designs to and from Cadence Virtuoso and Synopsys Custom Compiler.
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Automatic Constraints Compiler & Manager
ConMan
ConMan is the first commercially available formal constraints compiler tool that automatically generates SDC for any level of hierarchy and for any mode of a SoC, thereby significantly shortening the timing closure cycle. ConMan provides an intuitive means of automatically compiling and managing sign-off quality correct-by-construction timing constraints for all applications.
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Cross Development Tools
ColdFire V1
All Cosmic C Cross Compilers for Windows include IDEA - Cosmic's own integrated development environment which is preconfigured for the ColdFire family of processors. IDEA is designed specifically for developing embedded applications with Cosmic compilers. IDEA integrates an editor, project manager, graphical smart build/make facility, program analyzer, link file generator, documentation manager and ZAP debugger into one easy to use environment running under all popular Windows versions. Click here for more information about IDEA.
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Wireless Fiber Inspection Probe
OCI-20BN-W
OCI-20BN-W is a portable optical fiber connector inspector for checking fiber and connector end-face cleanliness, ideal for bench top and fiber optic network installation technicians to eliminate error caused by poor quality or improper cleaning.OCI-20BN-W offers excellent viewing on connector/fiber end-face and is able to feature to record and save image/video of fiber end-face; It can be connected to PC or phone by WIFI.More than 40 assorted high-precision tips designed for inspection solutionsAngled/Lengthened tips for awkward positions.Connect smart phone for testing FiberEye2 is the application on an android or IOS smart phone to capture, display and record the fiber end-face image from the Wi-Fi probe.Connect tablet/laptop for testing EFD is the analysis software on Windows tablet/laptop to have dusts, and scratches on end face inspected, analyzed, compiled and reported
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The Imperas Instruction Set Simulator
ISS
The Imperas ISS is often the first simulation product used in an embedded software development project. The Imperas ISS allows the development and debug of code for the target architecture on an x86 host PC with the minimum of setup and effort. It simply requires the cross compilation of your application and running the ISS with an argument to specify the name of the application object.
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Developer's Studio for ATLAS
PAWS
PAWS Developer's Studio gives you the power to compile, modify, debug, document, and simulate the operation of ATLAS test programs in a Windows environment.
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Harmonics And Flicker Measuring System
ProfLine Series
The Teseq ProfLine system is a complete and cost effective Harmonics and Flicker measurement test system which compiles to the latest IEC/EN standards, including IEC 61000-3-2 and IEC 61000-3-3. The programmable power generation capability of up to 45 kVA (90 kVA and 145 kVA sources comprise multiple 45 kVA units) provides more than ample power to cater for a wide range of Equipment Under Test (EUT).
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Fluid Analysis Information Management System
LubeTrak
LubeTrak compiles individual MicroLab oil reports into a consolidated database of historical information. This allows fleet managers to view and manage their MicroLab oil analysis results across the entire fleet. This fleet-level view can be used to assess the health of the entire fleet to optimize maintenance program and practices.
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SNMP Agent Testing & Debugging Suite
SNMP Inquistor
An SNMP Agent Development process inevitably involves testing and debugging activities that are tedious and time consuming. To save time and money on this development phase and to ensure that the developed responder's software is compliant with the SNMP standards, LogiSoft AR Ltd. came up with the SNMP Inquisitor, an easy to use, intuitive and comprehensive application suite that includes: MIB Compiler, SNMP Inquisitor Application and SNMP Sender Utility.
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64-Axis PCIe EtherCAT Master Motion Controller
PCIe-8338
ADLINK PCIe-8338 is a hardware-based EtherCAT motion controller able to support up to 64 synchronized axes and over 10,000 points simultaneously. The PCIe-8338 features dedicated isolated emergency stop input (EMG), and configurable isolated high-speed digital input as not only generic sensor input but also pulsar input, with up to 1MHz input frequency. Optimum jitter control is provided in minimal cycles of 250µs to optimize synchronous I/O performance for vertical automation applications in semiconductor, electronic manufacturing, and others. The PCIe-8338 provides an out-of-shell application-ready (APS) function library to generate multi-dimensional, highly synchronized, time-deterministic event-triggered motion & I/O control. A wide range of compatible 3rd party slaves are easily designed with ADLINK's APS function library. ADLINK's MotionCreatorPro 2 utility is fully compliant with the Microsoft Windows environment, that allows complete EtherCAT motion and I/O configuration and function evaluation as well as compiling program download functions.
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Professional ATLAS WorkStation
PAWS Developer's Studio
We can provide and fully support PAWS (Professional ATLAS WorkStation), the leading ATLAS development system used by most of the US and European military ATLAS based ATS. The PAWS suite includes full development systems as well as runtime only versions for executing previously developed TPS on an installed base of workshop systems.PAWS Developer's Studio gives you the power to compile, modify, debug, document, and simulate the operation of ATLAS test programs in a modern Windows environment. It offers the visual development capabilities prevalent in the marketplace today specifically tailored for ATLAS TPS development. A full range of the most commonly used ATLAS subsets is supported. A PAWS Toolkit can modify the ATLAS subset to meet the particular ATE (Test Station) configuration. Its output is ready to be executed on the associated debugging PAWS run time system.
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Integrated Development Environment
All Cosmic C Cross Compilers for Windows include IDEA - Cosmic's own integrated development environment which is preconfigured for the the compiler it comes with. IDEA is designed specifically for developing embedded applications with Cosmic compilers. IDEA integrates an editor, project manager, graphical smart build/make facility, program analyzer, link file generator, documentation manager and ZAP debugger into one easy to use environment running under Windows Windows 7, XP and compatible. IDEA includes the following features:
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Ada Development Environment
GNAT Pro
GNAT Pro is a robust and flexible Ada development environment. It comprises a full Ada compiler (Ada 83, Ada 95, and Ada 2005 features) based on the GNU GCC technology, an Integrated Development Environment (GNAT Programming Studio), a comprehensive toolsuite including a visual debugger, and a set of libraries and bindings.
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Stand-alone Software
N4391AU
The analysis software from the N4391A optical modulation analyzer can be used on your PC without any instrumentation. It offers all the analysis capabilities of the N4391A including its advanced signal processing algorithms for complex modulated optical signals. Use this software to process and analyze raw data stored as .sdf, .mat or .csv files from N4391A or N4392A measurements. This capability allows you to work with the data as if you would work directly in front of the instrument. It is an excellent tool for developing your own signal processing algorithms and testing them off-line, together with your MATLAB compiler. In addition, this software is an effective tool for learning basic and advanced concepts of complex optical modulation, based on stored files.
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FPGA PXI High-Performance Digital I/O Card
GX3700
The GX3700 is a user configurable, FPGA-based, 3U PXI card which offers 160 digital I/O signals which can be configured for single-ended or differential interfaces. The card employs the Altera Stratix III FPGA, which can support SerDes data rates up to 1.2 Gb/s, digital I/O clock rates of 700 MHz, and features 47,500 logic elements and 2.1 kb of memory. The GX3700 is supplied with an integral expansion board providing access to the FPGA’s 160 I/Os. Alternatively, users can design their own custom expansion cards for specific applications - eliminating the need for additional external boards which are cumbersome and physically difficult to integrate into a test system. The design of the FPGA is done by using Altera’s free Quartus II Web Edition tool set. Once the user has compiled the FPGA design, the configuration file can be loaded into the FPGA directly or via an on-board EEPROM.
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SpaceWire LabVIEW Driver VISA
137
STAR-Dundee's SpaceWire LabVIEW VISA driver has been implemented as a native LabVIEW driver, providing support for the STAR-Dundee PCI family of devices. Software written to control these devices may be deployed on any hardware platform that supports cPCI/PCI and NI-VISA, including both Windows based hosts and LabVIEW Real-Time targets, without requiring modifications to source code. The software is provided as LabVIEW source with password protected block diagrams, allowing users to compile for any target.
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Deep Packet Inspection
FlowPro
FlowPro is inserted into areas of the network when visibility is needed. It uses a deep packet inspection (DPI) to compile a flow cache, and exports traffic and threat details reflecting 100% of all communications that pass by. FlowPro is a great complement to the Scrutinizer Incident Response System and ensures the security team has insight where they need it.
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SystemVerilog, VHDL & Unified Power Format (UPF) Parser Platforms
Verific Design Automation, Inc.
SystemVerilog (which includes Verilog 2001) and VHDL are parsed and processed in two steps, analysis and elaboration. Mixed VHDL and SystemVerilog compilation is fully supported. UPF is processed in a single step, analysis.
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Simulink models run on ADwin
ADsim
With ADsim, you easily run Simulink models on ADwin hardware. With a few clicks only, you insert inputs and outputs for the ADwin system as blocks into the model and start C code generation. After compilation, the model runs on the ADwin system in real-time with absolute timing precision and predictability reaching sample rates up to 100 kHz.
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Elvior TestCast
TTCN-3
Elvior TestCast is a TTCN-3 test development and execution platform which includes TTCN-3 editor, TTCN-3 compiler and TTCN-3 executive. TestCast can be used for testing software or hardware components in a wide range of industry sectors. Candidate systems for testing with TestCast can be found from the industry sectors where TTCN-3 is widely used as an accepted generic test language - telecommunication, IOT, transport and automotive, military and defense. TestCast is ideal for incremental project development. It can be used for testing of an individual task or process. One can continue with the integration tests of a subsystem consisting of processes and later to integrate those subsystems and test them together as a whole software subsystem. It is even possible to continue to perform software/hardware integration tests where TestCast can be used to test software embedded in target hardware.
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Development System
FE-900
# Emulates Philips P89LPC932 Microcontrollers# Real-Time and Transparent Emulation up to 12MHz# 8K Emulation Memory# Real-Time Trace# Uses Philips Bond-Out Technology# Ceibo Windows Debugger and Keil uVision2# High-Level Support for all C/C++ Compilers and Assemblers# On-Line Assembler and Disassembler# Target Board, ISP Programmer and Power Supply Included# PLCC-28 Emulator Plug Included (TSSOP-28 Optional)
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Smart Analysis for PHP
PHPSA
PHPSA is a development tool aimed at bringing complex analysis for PHP applications and libraries.*Static analysis*Code metrics*Branch prediction*Sandbox (AST) Compiler
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Lattice SensAI Studio
Graphical interface based tool to help users built accelerated machine learning applications quickly. Select from a range of models pretrained to cover popular use cases, bring in your own data for additional training, validation the quality of training using TensorBoard, compile for Lattice’s FPGAs*Model Zoo with variety of models based on multiple architecture*Easy to use labeling, training, and compilation GUI*Docker container provided for installation on your own machine or server*Free license
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ISO/ANSI Compliance
The ANSI and ISO/IEC standard for the C Programming Language specifies that there are two forms of conforming compiler implementations: hosted and freestanding.
