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Verification IP
test and verify SoC's protocols and interface buses.
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IP Reuse
IC Manage Global Design Platform (GDP & GDP-XL) includes an open platform for maximizing IP reuse. Design and verification teams can use the system to rapidly publish and integrate IP into existing flows, and to trace bug dependencies. Internal and third party IP can be imported or linked with IP Central from multiple commercial and open source design management systems, as well as internal revision control systems. ”
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Waterproof Test Chamber
JL-XC
JL-XC series waterproof test chamber is mainly used for small electronic and electrical products. Such as lamps, electrical cabinets, electrical components and so one. The products are tested for physical and other related properties under simulated climatic conditions. After the test, it is judged whether the performance of the product meets the requirements by verification, so as to be used in the design, improvement, verification and factory inspection of the product. Comply with IEC60529:2001 《Degrees of protection provided by enclosures (IP Code)》, GB4208-2008 《Shell Protection Grade (IP Code)》 14.2.8 Terms and GB7000.1 《Lamps Part 1: General Requirements and Tests》 9.2.9 Terms.
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Field Ttesters
Our product range comprises from small handheld, battery fed testers to full featured service performance assurance tools and distributed monitoring systems. We have several product lines including:QoS / SLA verification system Ethernet, IP, Critical Data, VoIP, IPTV .Hand-held testers: Gigabit Ethernet, Synchronous Ethernet, E1, PDH, SDH, Ethernet, IP, Jitter, Wander, Datacom, Frame Relay, etc.
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EMBEDDED MMC (EMMC)
SD 3.0 / eMMC 4.51 IP Family
The eMMC Host IP is an RTL design in Verilog that implements an MMC / eMMC host controller in an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan MMC / eMMC Host IP Core has been widely used in different MMC applications by major semiconductor vendors with proven silicon.
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MIPI Total Display IP Solution
DSI
The Arasan MIPI Display Serial Interface (DSI) Controller IP provides both device and host functionality. Additionally, the DSI Controller provides a high-speed serial interface between an application processor and display and follows a rigorous verification methodology to ensure interoperability of our DSI digital controller with our D-PHY analog IP. Arasan’s DSI solutions are MIPI standards-compliant and are designed to accelerate integration, lower risk and accelerate time to market for developers of display applications. Arasan’s expertise is backed by our unique silicon proven design discipline and product development process that ensures fast silicon success with our analog and digital IP.
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MIPI Soundwire Total IP Solutions
Soundwire
Soundwire is suited for small, cost-sensitive audio peripherals such as modern digital class-D amplifiers and digital microphones. The Total MIPI SoundWire IP Solution from Arasan enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code for Master and Slave, fully validated for compliance with the standard, a comprehensive test environment with a compliance suite for verification of the IP package, a SoundWire Hardware Development Kit (“HDK”) for FPGA prototyping, a SoundWire protocol analyzer and a complete SoundWire software stack.
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Emulation Platform
Veloce
The Veloce® Emulation Platform dramatically reduces risk in the verification of today’s complex SoCs and is a core technology in the Mentor Enterprise Verification Platform™ (EVP). Mentor’s software and application solutions and continual enhancements enable a comprehensive verification environment for IP, chip, and system level verification.
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Analyze RTL
ASICs and FPGA routinely have millions of gates with memories, transceivers, third party IP and processor cores. Problems can be time consuming and complex to debug in the lab and through simulations. Designers need verification tools that can identify problems quickly to reduce their verification and debug time before simulation, before synthesis, and definitely before burning chips in the lab.
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Ethernet Testing Network Performance
Networked Communication Solutions, LLC
Xena Networks and Veryx Technologies have created an innovative Ethernet test platform that combines Xena’s high performance, wire-speed Ethernet test hardware with Veryx’s broad portfolio of IP & Ethernet functional and conformance test suites. The result: an affordable, high-performance platform for IP & Ethernet load stress, protocol conformance & functional verification testing.
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ADSL / 2 / 2+ Handheld VoIP Tester
QuickTest 500
*Rapid Testing. The QuickTest 500 ADSL2+ Tester's automatic Service Verification Test Suite starts as soon as you switch on (results are typically obtained in less than 3 minutes)*Simple to use. Virtually no product training required with QuickTest 500 ADSL Tester*Configurable Pass / Fail Indicators on the LCD display and clearly presented in multi-colour LEDs on the front panel*No need to get a laptop out*Save and name up to 16 test results at any one time*Line Voltage LED indicates poor, missing or excessive Line Voltage*ADSL/2/2+ Test LEDs to indicate if ADSL Showtime achieved*In Service LED indicates problems with PPP or IP layer*LEDs to indicate problems with the Trained Line Rate, poor Noise Margin or excessive Line Attenuation
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SoC Verification
TrekSoC
TrekSoC automatically generates self-verifying C test cases to run on the embedded processors in SoCs. This verifies your chips more quickly and more thoroughly than an external testbench, hand-written C tests, or running only production code on the processors. TrekSoC's generated test cases target all aspects of full-SoC verification and work in a variety of different environments.
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IP Cores
logicBRICKS IP Cores by Xylon - for applications including compact multilayer video controller, versatile video input, multiview 3D transformation engine, image signal processing (isp) ulstraHD pipeline, high dynamic range pipeline, scalable 3d graphics accelerator, DDR3 SDRAM Memory Controller, slave hssl controller, HDR image signal processing framework, video design framework for multi-camera vision applications, and more
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IC Design & Verification
Mentor Graphics provides best-in-class products for IC design. Calibre for physical verification, extraction, resolution enhancement and mask data preparation, ADVance MS for analog/mixed-signal simulation and an integrated tool flow for custom IC design
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IP Converters
SMPTE-2022 compliant standalone solutions for conversion between IP and "traditional" DTV signals such as ASI and QAM. These IP converters are hardware-based, providing low latency and zero-jitter transmission of IP signals.
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Phase Verification Bridges
5002
Clarke-Hess Communications Research
The Model 5002 Phase Verification Bridge set comprises passive devices that are used in conjunction with Model 5500-2 Phase Standard and an output null indicator such as a true rms voltmeter, an oscilloscope or a wave analyzer to verify that the Phase Standard is continuing to operate within its specified phase accuracy limits.
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Verification IP's
SmartDV Technologies India Private Limited
We develop Verification Components, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our VIP''s are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.
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Foundation IP
TSMC
Our Foundation IPs embed power management features (multi-Vt/multi-channel libraries, multi-VDD characterization, integrated power-switches, source-biasing…) which allow designers to explore the SoC architecture. Optimal configurations can be generated to meet the application’s Performance, Power and Area constraints. We also complement our offering to reach best-in-class Energy Efficient SoC by serving Always-On power-domains with a dedicated offer, optimized to achieve the ultra-low-power requirements of battery-operated devices in sleep mode.
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Pegasus Verification System
The Cadence® Pegasus® Verification System is a cloud-ready physical verification signoff solution, which enables engineers to deliver advanced-node integrated circuits (ICs) to market faster. The groundbreaking technology delivers up to 10X improved performance on DRC runs and reduces turnaround time from days to hours.
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Pack (IP) Modules
IP & MM
Industry Pack (IP) modules are international standards as per ANSI-VITA 4.These are mezzanine modules of approximately the size of a business card (99mm x 45mm). Featuring a 16 or 32 bit wide I/O interface and 50 user defined I/O pins, these modules are ideal for providing the capability for high density I/O.IP carriers provide multiple slots on a single carrier. This allows multiple IP modules to be provided on a single slot in a Compact PCI / VME / VXI / PCI card cage.Industry Pack modules provide some unique advantages in system integration. These include:
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LSI Functional Verification Services
SpecInsight
The keys to functional verification are “verification strategy” and “highly complete verification item extraction.” Our functional verification services emphasize highly complete verification item extraction while also generating test benches and functional scenarios, random verification, and even functional coverage to meet customer demands by providing these services from a wide variety of angles. By implementing functional verification on the RTL and C models designed by customers from a third-party perspective, we improve quality of customers’ circuits.
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Process Verification with Augmented Reality
PVS AR
Connected to our standard, open PVS (Process Verification System) platform, the new early adopter PVS AR system, allows users to do several things, not yet seen in the industry. First, by connecting to a wide variety of standard torque tools, standard PVS connectivity allows customer choice to pick the right tool for the right job, but now allows these tools to be used in an augmented reality framework.
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IP QAM
SHP200D
Hangzhou Softel Optic Co., Ltd.
SHP200D 10G IP QAM processor is an all-in-one device developed by SOFTEL which integrates multiplexer, scrambler and modulator in one body with maximum 112 DVB-C QAM channels output. With 10G switch built in, it can process 10G optical signal to work as a traditional QAM modulator. This processor is equipped with 2 card slots to load 32ch or 48ch or 64ch QAM card. Its high density helps operators to save cost to the most extent.
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FPGA Verification
The market is changing and rapidly expanding for FPGAs. Advancements in higher design frequency, embedded system FPGAs, and lower power consumption, combined with the reprogrammable advantages of FPGAs are increasing adoption into applications that have typically been enabled with ASSP/SoCs, including AI/ML, 5G, crypto, data center and high-performance computing applications.
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Content Verification System
Pulsar
Pulsar is an automated content verification system for stored media files. It is designed for use by Broadcasters, Service Providers, Content Creators and Optical Media replicators allowing them to analyze the content before it is put live or stamped on the optical media. The software performs conformance and quality analysis on the streams provided. It allows definition of a range of user-defined checks to be performed as part of the Analysis.
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IP Solution
eMMC 5.1
Demand for mobile content capacity and bandwidth for video, pictures and music is ever increasing. To address this demand in the next generation of smartphones, tablets, and portable devices, the eMMC 5.1 Specification from JEDEC, improves the current HS400 speeds operating at 3.2Gbps, with "command queuing" making the data transfers highly efficient by offloading the software overhead into the controller. eMMC 5.1 further improves the reliability of operation by utilizing an "enhanced strobe" at the PHY layer. The eMMC5.1 is backward compatible with the existing eMMC 4.51 and eMMC 5.0 Devices.
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Multi Channel Optical Fibre Verification
The multi-channel optical fibre test system is used in the development and qualification of single mode optical fibres. The fibres are exposed to environmental influences in a climatic chamber in order to analyse the data on insertion loss and reflection. In addition, the current temperature in the climatic chamber is documented. Insertion loss measurement is performed with the help of an optical power meter, laser sources and optical switches. An Optical Time Domain Reflectometer (OTDR) from Exfo is used for the reflection measurements. The system was designed for the simultaneous characterization of 15 sample fibres and one reference fibre.
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Functional Verification Platform
Riviera-PRO
Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.
